* Mathieu Desnoyers: > Basically, the use-cases targeted are those where some cores on the > system support a larger instruction set than others. So for instance, > some cores could use a faster atomic add instruction than others, > which should rely on a slower fallback. This is also the same story > for reading the performance monitoring unit counters from user-space: > it depends on the feature-set supported by the CPU on which the > instruction is issued. Same applies to cores having different > cache-line sizes.
The kernel needs to present a consistent view to userspace, the common denominator. I don't think there is any other way. The situation is not new at all, by the way. It also arises with VM and process migration. In glibc, we do not re-run CPU feature selection upon resume (and how could we? function pointers would have to change), and we have no plans to implement anything differently. Thanks, Florian
