On Tue, Nov 13, 2018 at 12:36:20PM +0000, Shameerali Kolothum Thodi wrote:
> > @@ -156,9 +156,9 @@ static void pcie_do_write_cmd(struct controller *ctrl,
> > u16 cmd,
> > slot_ctrl |= (cmd & mask);
> > ctrl->cmd_busy = 1;
> > smp_mb();
> > + ctrl->slot_ctrl = slot_ctrl;
>
> Actually I tried this one, but it doesn't help in this case as the initial
> pcie_capability_read_word() returns the slot_ctrl without PCI_EXP_SLTCTL_HPIE
> bit set. It looks to me pcie_enable_notification() function enables this,
>
> if (!pciehp_poll_mode)
> cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
>
> I don't know this is as per the spec or not as the initial cap read doesn't
> seems to
> have the PCI_EXP_SLTCTL_HPIE bit set.
If I read the code right cmd value should end up in ctrl->slot_ctrl
properly from pcie_enable_notification().
However, I think we are missing check for PCI_EXP_SLTCTL_CCIE in
pciehp_isr().
Here's an updated patch, can you try and see if it makes any difference?
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 7dd443aea5a5..da2cbe892444 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -156,9 +156,9 @@ static void pcie_do_write_cmd(struct controller *ctrl, u16
cmd,
slot_ctrl |= (cmd & mask);
ctrl->cmd_busy = 1;
smp_mb();
+ ctrl->slot_ctrl = slot_ctrl;
pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
ctrl->cmd_started = jiffies;
- ctrl->slot_ctrl = slot_ctrl;
/*
* Controllers with the Intel CF118 and similar errata advertise
@@ -522,7 +522,7 @@ static irqreturn_t pciehp_isr(int irq, void *dev_id)
* in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
*/
if (pdev->current_state == PCI_D3cold ||
- (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
+ (!(ctrl->slot_ctrl & (PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE))
&& !pciehp_poll_mode))
return IRQ_NONE;
/*
