[Patch v7 07/18] x86/speculation: Reorganize speculation control MSRs update

[Tim Chen]

The logic to detect whether there's a change in the previous
and next task's flag relevant to update speculation control
MSRs are spread out across multiple functions.

Consolidate all checks needed for updating speculation
control MSRs to __speculation_ctrl_update().

This makes it easy to pick the right speculation control MSR,
and the bits in the MSR that needs updating based on
TIF flags changes.

Originally-by: Thomas Lendacky <thomas.lenda...@amd.com>
Signed-off-by: Tim Chen <tim.c.c...@linux.intel.com>
---
 arch/x86/kernel/process.c | 44 +++++++++++++++++++++++++++++++++-----------
 1 file changed, 33 insertions(+), 11 deletions(-)

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 8aa4960..74bef48 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -397,25 +397,48 @@ static __always_inline void 
amd_set_ssb_virt_state(unsigned long tifn)
 
 static __always_inline void spec_ctrl_update_msr(unsigned long tifn)
 {
-       u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
+       u64 msr = x86_spec_ctrl_base;
+
+       /*
+        * If X86_FEATURE_SSBD is not set, the SSBD
+        * bit is not to be touched.
+        */
+       if (static_cpu_has(X86_FEATURE_SSBD))
+               msr |= ssbd_tif_to_spec_ctrl(tifn);
 
        wrmsrl(MSR_IA32_SPEC_CTRL, msr);
 }
 
-static __always_inline void __speculation_ctrl_update(unsigned long tifn)
-{
-       if (static_cpu_has(X86_FEATURE_VIRT_SSBD))
-               amd_set_ssb_virt_state(tifn);
-       else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
-               amd_set_core_ssb_state(tifn);
-       else
+/*
+ * Update the MSRs managing speculation control during context switch.
+ *
+ * tifp: previous task's thread flags
+ * tifn: next task's thread flags
+ */
+static __always_inline void __speculation_ctrl_update(unsigned long tifp,
+                                                     unsigned long tifn)
+{
+       bool updmsr = false;
+
+       /* If TIF_SSBD is different, select the proper mitigation method */
+       if ((tifp ^ tifn) & _TIF_SSBD) {
+               if (static_cpu_has(X86_FEATURE_VIRT_SSBD))
+                       amd_set_ssb_virt_state(tifn);
+               else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
+                       amd_set_core_ssb_state(tifn);
+               else if (static_cpu_has(X86_FEATURE_SSBD))
+                       updmsr  = true;
+       }
+
+       if (updmsr)
                spec_ctrl_update_msr(tifn);
 }
 
 void speculation_ctrl_update(unsigned long tif)
 {
+       /* Forced update. Make sure all relevant TIF flags are different */
        preempt_disable();
-       __speculation_ctrl_update(tif);
+       __speculation_ctrl_update(~tif, tif);
        preempt_enable();
 }
 
@@ -451,8 +474,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct 
task_struct *next_p,
        if ((tifp ^ tifn) & _TIF_NOCPUID)
                set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
 
-       if ((tifp ^ tifn) & _TIF_SSBD)
-               __speculation_ctrl_update(tifn);
+       __speculation_ctrl_update(tifp, tifn);
 }
 
 /*
-- 
2.9.4