As done in the Rockchip vendor tree and also on other
"arm,armv7-timer" instances, the correct GIC_CPU_MASK_SIMPLE mask
is 4 instead of 1.

Signed-off-by: Otavio Salvador <ota...@ossystems.com.br>
Signed-off-by: Fabio Berton <fabio.ber...@ossystems.com.br>
---

 arch/arm/boot/dts/rv1108.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index c7a26f82655b..7b331766120d 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -71,8 +71,8 @@
 
        timer {
                compatible = "arm,armv7-timer";
-               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 
IRQ_TYPE_LEVEL_HIGH)>,
-                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 
IRQ_TYPE_LEVEL_HIGH)>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 
IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 
IRQ_TYPE_LEVEL_HIGH)>;
                clock-frequency = <24000000>;
        };
 
-- 
2.19.1

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