Quoting Taniya Das (2018-11-21 23:53:41) > diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c > index f133b7f..ba8ff99 100644 > --- a/drivers/clk/qcom/gcc-sdm845.c > +++ b/drivers/clk/qcom/gcc-sdm845.c > @@ -3153,6 +3153,34 @@ enum { > }, > }; > > +static struct clk_branch gcc_lpass_q6_axi_clk = { > + .halt_reg = 0x47000, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x47000, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_lpass_q6_axi_clk", > + .flags = CLK_IS_CRITICAL, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gcc_lpass_sway_clk = { > + .halt_reg = 0x47008, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x47008, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_lpass_sway_clk", > + .flags = CLK_IS_CRITICAL, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct gdsc pcie_0_gdsc = { > .gdscr = 0x6b004, > .pd = { > @@ -3453,6 +3481,8 @@ enum { > [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, > [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, > [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, > + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, > + [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
I have one single idea to avoid the integration nightmare with dts needing another update for this on platforms where these can't be touched. It's not perfect, but we can throw these clks and usage of the clks behind an #ifdef CONFIG_SDM_LPASSCC_845 and then let the dts parts match up with the clk driver parts in linux-next. After everything is merged together, someone can turn on the knobs for LPASS clk controller and make sure they have the right dts bits to mark them as protected.