Quoting A.s. Dong (2018-11-14 05:01:47) > The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System > Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. > > NOTE pfdv2 can only be operated when clk is gated. > > Cc: Stephen Boyd <sb...@codeaurora.org> > Cc: Michael Turquette <mturque...@baylibre.com> > Cc: Shawn Guo <shawn...@kernel.org> > Cc: Anson Huang <anson.hu...@nxp.com> > Cc: Bai Ping <ping....@nxp.com> > Signed-off-by: Dong Aisheng <aisheng.d...@nxp.com> > > ---
Applied to clk-next
