Quoting A.s. Dong (2018-11-14 05:01:47) > The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System > Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. > > NOTE pfdv2 can only be operated when clk is gated. > > Cc: Stephen Boyd <[email protected]> > Cc: Michael Turquette <[email protected]> > Cc: Shawn Guo <[email protected]> > Cc: Anson Huang <[email protected]> > Cc: Bai Ping <[email protected]> > Signed-off-by: Dong Aisheng <[email protected]> > > ---
Applied to clk-next
