Quoting A.s. Dong (2018-11-14 05:01:43) > pllv4 is designed for System Clock Generation (SCG) module observed > in IMX ULP SoC series. e.g. i.MX7ULP. > > The SCG modules generates clock used to derive processor, system, > peripheral bus and external memory interface clocks while this patch > intends to support the PLL part. > > Cc: Stephen Boyd <[email protected]> > Cc: Michael Turquette <[email protected]> > Cc: Shawn Guo <[email protected]> > Cc: Anson Huang <[email protected]> > Cc: Bai Ping <[email protected]> > Signed-off-by: Dong Aisheng <[email protected]> > > ---
Applied to clk-next
