* Thomas Gleixner <[EMAIL PROTECTED]> wrote:
> The other question is:
>
> Is the driver confused by the resent irq or is the chip-set unhappy
> about the resend ?
>
> We could figure the latter out by activating the software based resend
> method.
yeah. The patch below enables sw-resend on x86, to test the theory
whether the APIC-driven hardware-vector-resend code has some problem.
Marcin, could you please give this one a try too? Good behavior would be
a fully working kernel (no hung device) with no extra kernel messages.
Bad behavior would be any extra kernel message or any non-working
device.
Ingo
----------------------------->
Subject: x86: activate HARDIRQS_SW_RESEND
From: Ingo Molnar <[EMAIL PROTECTED]>
activate the software-triggered IRQ-resend logic.
it appears some chipsets/cpus do not handle local-APIC driven IRQ
resends all that well, so always use the soft mechanism to trigger
the execution of pending interrupts.
Signed-off-by: Ingo Molnar <[EMAIL PROTECTED]>
---
arch/i386/Kconfig | 4 ++++
kernel/irq/manage.c | 8 ++++++++
2 files changed, 12 insertions(+)
Index: linux/arch/i386/Kconfig
===================================================================
--- linux.orig/arch/i386/Kconfig
+++ linux/arch/i386/Kconfig
@@ -1270,6 +1270,10 @@ config GENERIC_PENDING_IRQ
depends on GENERIC_HARDIRQS && SMP
default y
+config HARDIRQS_SW_RESEND
+ bool
+ default y
+
config X86_SMP
bool
depends on SMP && !X86_VOYAGER
Index: linux/kernel/irq/manage.c
===================================================================
--- linux.orig/kernel/irq/manage.c
+++ linux/kernel/irq/manage.c
@@ -181,6 +181,14 @@ void enable_irq(unsigned int irq)
desc->depth--;
}
spin_unlock_irqrestore(&desc->lock, flags);
+#ifdef CONFIG_HARDIRQS_SW_RESEND
+ /*
+ * Do a bh disable/enable pair to trigger any pending
+ * irq resend logic:
+ */
+ local_bh_disable();
+ local_bh_enable();
+#endif
}
EXPORT_SYMBOL(enable_irq);
-
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