Quoting Jorge Ramirez-Ortiz (2018-12-17 01:46:27) > The high frequency pll functionality is required to enable CPU > frequency scaling operation. > > Co-developed-by: Niklas Cassel <[email protected]> > Signed-off-by: Niklas Cassel <[email protected]> > Signed-off-by: Jorge Ramirez-Ortiz <[email protected]> > --- > arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi > b/arch/arm64/boot/dts/qcom/qcs404.dtsi > index 4594fea7..ec3f6c7 100644 > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi > @@ -375,6 +375,15 @@ > #mbox-cells = <1>; > }; > > + apcs_hfpll: clock-controller@0b016000 {
Drop leading 0 on unit address please. > + compatible = "qcom,hfpll"; > + reg = <0x0b016000 0x30>; Wow that is small! > + #clock-cells = <0>; > + clock-output-names = "apcs_hfpll"; > + clocks = <&xo_board>; > + clock-names = "xo"; > + }; > +
