From: Yixun Lan <yixun....@amlogic.com> Export the emmc sub clock phase delay ops which will be used by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan <yixun....@amlogic.com> Signed-off-by: Jianxin Pan <jianxin....@amlogic.com> --- drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-phase-delay.c | 73 +++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc.h | 7 ++++ 3 files changed, 81 insertions(+) create mode 100644 drivers/clk/meson/clk-phase-delay.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index acd8694..d59620d 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o vid-pll-div.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase-delay.o obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o obj-$(CONFIG_COMMON_CLK_AMLOGIC) += sclk-div.o obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o diff --git a/drivers/clk/meson/clk-phase-delay.c b/drivers/clk/meson/clk-phase-delay.c new file mode 100644 index 0000000..a6e6600 --- /dev/null +++ b/drivers/clk/meson/clk-phase-delay.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson MMC Sub Clock Controller Driver + * + * Copyright (c) 2017 Baylibre SAS. + * Author: Jerome Brunet <jbru...@baylibre.com> + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yixun Lan <yixun....@amlogic.com> + * Author: Jianxin Pan <jianxin....@amlogic.com> + */ + +#include <linux/clk-provider.h> +#include "clkc.h" + +static inline struct meson_clk_phase_delay_data * +meson_clk_get_phase_delay_data(struct clk_regmap *clk) +{ + return clk->data; +} + +static int meson_clk_phase_delay_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_delay_data *ph; + unsigned long period_ps, p, d; + int degrees; + + ph = meson_clk_get_phase_delay_data(clk); + p = meson_parm_read(clk->map, &ph->phase); + degrees = p * 360 / (1 << (ph->phase.width)); + + period_ps = DIV_ROUND_UP_ULL(NSEC_PER_SEC * 1000ull, + clk_hw_get_rate(hw)); + + d = meson_parm_read(clk->map, &ph->delay); + degrees += d * ph->delay_step_ps * 360 / period_ps; + degrees %= 360; + + return degrees; +} + +static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_delay_data *ph; + unsigned long period_ps, d = 0; + unsigned int p; + + ph = meson_clk_get_phase_delay_data(clk); + period_ps = DIV_ROUND_UP_ULL(NSEC_PER_SEC * 1000ull, + clk_hw_get_rate(hw)); + + /* + * First compute the phase index (p), the remainder (r) is the + * part we'll try to acheive using the delays (d). + */ + p = 360 / 1 << (ph->phase.width); + degrees = degrees / p; + d = DIV_ROUND_CLOSEST((degrees % p) * period_ps, + 360 * ph->delay_step_ps); + d = min(d, PMASK(ph->delay.width)); + + meson_parm_write(clk->map, &ph->phase, degrees); + meson_parm_write(clk->map, &ph->delay, d); + return 0; +} + +const struct clk_ops meson_clk_phase_delay_ops = { + .get_phase = meson_clk_phase_delay_get_phase, + .set_phase = meson_clk_phase_delay_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 00b3320..e6f0905 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -118,6 +118,12 @@ struct clk_regmap _name = { \ }, \ }; +struct meson_clk_phase_delay_data { + struct parm phase; + struct parm delay; + unsigned int delay_step_ps; +}; + /* clk_ops */ extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; @@ -127,6 +133,7 @@ struct clk_regmap _name = { \ extern const struct clk_ops meson_clk_phase_ops; extern const struct clk_ops meson_vid_pll_div_ro_ops; extern const struct clk_ops meson_sclk_div_ops; +extern const struct clk_ops meson_clk_phase_delay_ops; struct clk_hw *meson_clk_hw_register_input(struct device *dev, const char *of_name, -- 1.9.1