On 04/01/2019 08:03, chunhui dai wrote: > fix the rate and divder of hdmi phy for MT2701. This is a bug? Then we would need a fixes tag. Otherwise you should explain in the commit, that you need to change the calculation due to previous commits. Regards, Matthias > > Signed-off-by: chunhui dai <chunhui....@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > index a28a32d..10b6235 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > @@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, > unsigned long rate, > > if (rate <= 64000000) > pos_div = 3; > - else if (rate <= 12800000) > - pos_div = 1; > + else if (rate <= 128000000) > + pos_div = 2; > else > pos_div = 1; > >
