On Wed, Jan 9, 2019 at 2:59 PM Josh Poimboeuf <jpoim...@redhat.com> wrote: > > NOTE: At least experimentally, the call destination writes seem to be > atomic with respect to instruction fetching. On Nehalem I can easily > trigger crashes when writing a call destination across cachelines while > reading the instruction on other CPU; but I get no such crashes when > respecting cacheline boundaries.
I still doubt ifetch is atomic on a cacheline boundary for the simple reason that the bus between the IU and the L1 I$ is narrower in older CPU's. Also, the fill of the L1 I$ from the (cache coherent L2) may not be a cacheline at a time either. That said, the fetch may be sufficiently ordered that it works in practice. It _would_ be absolutely lovely to be able to do things like this. I do agree with Nadav that if there's some way to avoid this, it would be good. I'm not in general a huge fan of compiler plugins (compiler instability is just about my worst fear, and I feel plugins tend to open up that area a lot), but it does feel like this might be something where compiler tweaking would possibly be the cleanest approach. Linus