On Wed, Jan 16, 2019 at 1:24 PM Fenghua Yu <fenghua...@intel.com> wrote: > > UMWAIT or TPAUSE called by user process makes processor to reside in > a light-weight power/performance optimized state (C0.1 state) or an > improved power/performance optimized state (C0.2 state). > > IA32_UMWAIT_CONTROL MSR register allows OS to set global maximum umwait > time and disable C0.2 on the processor. > > By default C0.2 is enabled so user wait instructions can enter the state > if user wants to save more power but wakeup time is slower. In some cases > e.g. real time, user wants to disable C0.2 and all C0.2 requests revert > to C0.1. > > A new "/sys/devices/system/cpu/umwait_control/umwait_enable_c0_2" file is > created to allow user to check if C0.2 is enabled or disabled and also > allow user to enable or disable C0.2. Value "0" in the file means C0.2 is > disabled. Value "1" means C0.2 is enabled.
Do you have any sense as to what the actual C0.2 entry and exit latency is? --Andy
