On Thu, Jan 17, 2019 at 03:55:17PM +0530, Balakrishna Godavarthi wrote: > Hi Matthias, > > On 2019-01-17 01:52, Matthias Kaehlcke wrote:
> >> - /* Wait for 100 uS for SoC to settle down */ > >> - usleep_range(100, 200); > >> + serdev_device_wait_until_sent(hu->serdev, timeout); > >> + /* Wait of 5ms is required for assuring to send the byte on the Tx > >> + * line and also for the controller to settle down for the received > >> + * byte. > >> + */ > >> + usleep_range(5000, 6000); > > > > I incorrectly claimed that there might be still bytes sitting in the > > UART FIFO when serdev_device_wait_until_sent() returns, Johan > > corrected me on that (thanks!). So if it takes the SoC 100us to settle > > down we should be good with the original code. > > [Bala]: sure will revert, i think he commented that wait_until_sent() > will only guarantee circular buffer is empty. if wait_until_sent() > guarantee us that the data was transmitted from the FIFO, then 100us > will work. No, Matthias is correct; I claimed that the UART FIFO will be empty (at least as long as flow control is disabled, otherwise it may never empty and we therefore also have a time out). Johan
