On Mon, Jan 21, 2019 at 11:13:00AM +0800, Yinbo Zhu wrote: > From: Suresh Gupta <b42...@freescale.com> > > PHY_CLK_VALID bit for UTMI PHY in USBDR does not set even > if PHY is providing valid clock. Workaround for this > involves resetting of PHY and check PHY_CLK_VALID bit > multiple times. If PHY_CLK_VALID bit is still not set even > after 5 retries, it would be safe to deaclare that PHY > clock is not available. > This erratum is applicable for USBDR less then ver 2.4. > > Signed-off-by: Suresh Gupta <b42...@freescale.com> > Signed-off-by: yinbo.zhu <yinbo....@nxp.com>
Same issue here with the signed-off-by name. For all of these patches. Please fix up and resend the whole series. thanks, greg k-h
