Ping... On 2019/01/07 22:21, Katsuhiro Suzuki wrote:
Custom approximation of fractional-divider may not need parent clock rate checking. For example Rockchip SoCs work fine using grand parent clock rate evne if target rate is greater than parent.This patch removes parent clock rate check from custom approximation. Signed-off-by: Katsuhiro Suzuki <katsuh...@katsuster.net> --- drivers/clk/clk-fractional-divider.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 545dceec0bbf..b0fc5509e0ff 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -79,13 +79,17 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long m, n; u64 ret;- if (!rate || rate >= *parent_rate)+ if (!rate) return *parent_rate;- if (fd->approximation)+ if (fd->approximation) { fd->approximation(hw, rate, parent_rate, &m, &n); - else + } else { + if (rate >= *parent_rate) + return *parent_rate; + clk_fd_general_approximation(hw, rate, parent_rate, &m, &n); + }ret = (u64)*parent_rate * m;do_div(ret, n);
