On 2/4/2019 11:15 AM, Peter Zijlstra wrote:
On Mon, Feb 04, 2019 at 10:43:41AM -0500, Liang, Kan wrote:
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1628,6 +1628,7 @@ void __init intel_ds_init(void)
        x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
        x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
        x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
+       x86_pmu.pebs_no_isolation = 1;

We will submit the Icelake support soon (probably next week).
That will be a problem for Icelake.

We can have ICL set it to 0 explicitly, but explicitly setting it to 1
_11_ times is just silly.

Also, what perfmon version will ICL have? If it were to be 5 we could
key off of that.


Right, we can use perfmon version here. I will apply it in V7.

Thanks,
Kan

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