On 2/1/19 9:14 PM, Fenghua Yu wrote: > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -221,6 +221,7 @@ > #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD > family 0x17 (Zen) */ > #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF > workaround PTE inversion */ > #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ > +#define X86_FEATURE_AC_SPLIT_LOCK ( 7*32+31) /* #AC for split lock */
The last time this was posted, we (Intel) promised to go get the proper (CPUID or MSR-based) enumeration of this feature documented. Did we do that? If so, where is that documentation?
