On Mon, Feb 04, 2019 at 11:05:52AM -0800, Dave Hansen wrote: > On 2/4/19 9:49 AM, Thomas Gleixner wrote: > > On Fri, 1 Feb 2019, Fenghua Yu wrote: > >> This option behaves like existing kernel option clearcpuid. > > > > No it does NOT. clearcpuid allows to disable things. > > > > This allows to enable random CPUID bits without any sanity checking. Not > > going to happen. We made it clear in the past that functionality needs to > > be detectable by enumeration. We do quirks for broken crap, but this is > > just not how it works. > > Hi Thomas, > > I think we are trying persuade you like mentioned here: > > > http://lkml.kernel.org/r/alpine.deb.2.21.1807122153170.1...@nanos.tec.linutronix.de > > But, we're not being very persuasive because we kinda forgot about the > "if and only if" condition that you mentioned.
Intel SDM published TODAY does have IA32_CORE_CAPABILITY MSR enumerateion bit CPUID.0x7.0:EDX[30] now. Please check today's SDM for the bit: https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4 I will add the two patches that enumerate the MSR and #AC for split lock in the next version. Thanks. -Fenghua
