[PATCH 8/9] ARM: dts: sun9i: a80-optimus: Enable GMAC

[Chen-Yu Tsai]

The A80 Optimus has a Realtek RTL8211E ethernet PHY which uses RGMII to
talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's
core logic and gpio1-ldo for I/O. The latter also powers the SoC side
pins. As there is no binding to model a second regulator supply for the
PHY, it is omitted. It is however properly modeled for the PIO.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts 
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 9c25176e69dc..864715ec3cb0 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -120,6 +120,19 @@
        status = "okay";
 };
 
+&gmac {
+       pinctrl-names = "default";
+       pinctrl-0 = <&gmac_rgmii_pins>;
+       phy = <&phy1>;
+       phy-mode = "rgmii";
+       phy-supply = <&reg_cldo1>;
+       status = "okay";
+
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+       };
+};
+
 &mmc0 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc0_pins>;
@@ -391,6 +404,14 @@
                                 */
                                regulator-min-microvolt = <3300000>;
                                regulator-max-microvolt = <3300000>;
+                               /*
+                                * The PHY requires 20ms after all voltages
+                                * are applied until core logic is ready and
+                                * 30ms after the reset pin is de-asserted.
+                                * Set a 100ms delay to account for PMIC
+                                * ramp time and board traces.
+                                */
+                               regulator-enable-ramp-delay = <100000>;
                                regulator-name = "vcc-gmac-phy";
                        };
 
-- 
2.20.1