On Wed, Feb 06, 2019 at 11:16:07AM -0800, Sowjanya Komatineni wrote: > This patch adds DMA support for Tegra I2C. > > Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for > transfer size of the max FIFO depth and DMA mode is used for > transfer size higher than max FIFO depth to save CPU overhead. > > PIO mode needs full intervention of CPU to fill or empty FIFO's > and also need to service multiple data requests interrupt for the > same transaction. This adds delay between data bytes of the same > transfer when CPU is fully loaded and some slave devices has > internal timeout for no bus activity and stops transaction to > avoid bus hang. DMA mode is helpful in such cases. > > DMA mode is also helpful for Large transfers during downloading or > uploading FW over I2C to some external devices. > > Signed-off-by: Sowjanya Komatineni <skomatin...@nvidia.com> > --- > [V14] : Switched back to use dma_alloc_coherent as it guarentees contiguous > device > dma address space. > Fixed FIFO Trigger level programming to construct value from scratch. > Previous versions does register read-modify-write without masking. > T20 has DVC offsets different to I2C. This version has fix to account > DVC > offset during dma slave configuration. > [V13] : T20 has DVC used for some power controls. This version has fix for > using > proper DVC register offsets for DMA programming incase when used in DMA > mode. > [V12] : Replaced dma_alloc_coherent with dma_alloc_attrs to force the > allocated > buffer to be contiguous also in physical memory as Tegra194 supports > max > 64K and dma_alloc_coherent doesnt guarentee contiguous memory. > Changed return code from EIO to EINVAL incase of failure to obtain dma > descriptor. > Fixed coding style check issues. > [V11] : Replaced deprecated dmaengine_terminate_all with > dmaengine_termine_async > from non-atomic context and dmaengine_terminate_sync from atomic > context. > Fixed to program fifo trigger levels properly when transfer falls back > to > pio mode in case of dma slave configuration failure and other minor > fixes. > [V10] : APBDMA is replaced with GPCDMA on Tegra186 and Tegra194 designs. > Added apbdma hw support flag to now allow Tegra186 and later use > APBDMA driver. > Added explicit flow control enable for DMA slave config and error > handling. > Moved releasing DMA resources to seperate function to reuse in > multiple places. > Updated to register tegra_i2c_driver from module level rather than > subsys > level. > Other minor feedback > [V9] : Rebased to 5.0-rc4 > Removed dependency of APB DMA in Kconfig and added conditional check > in I2C driver to decide on using DMA mode. > Changed back the allocation of dma buffer during i2c probe. > Fixed FIFO triggers depending on DMA Vs PIO. > [V8] : Moved back dma init to i2c probe, removed ALL_PACKETS_XFER_COMPLETE > interrupt and using PACKETS_XFER_COMPLETE interrupt only and some > other fixes > Updated Kconfig for APB_DMA dependency > [V7] : Same as V6 > [V6] : Updated for proper buffer allocation/freeing, channel release. > Updated to use exact xfer size for syncing dma buffer. > [V5] : Same as V4 > [V4] : Updated to allocate DMA buffer only when DMA mode. > Updated to fall back to PIO mode when DMA channel request or > buffer allocation fails. > [V3] : Updated without additional buffer allocation. > [V2] : Updated based on V1 review feedback along with code cleanup for > proper implementation of DMA. > > > drivers/i2c/busses/i2c-tegra.c | 411 > ++++++++++++++++++++++++++++++++++++----- > 1 file changed, 367 insertions(+), 44 deletions(-)
Acked-by: Thierry Reding <tred...@nvidia.com>
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