On 31/01/19 7:09 PM, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <[email protected]> > > I've been unable to figure out exactly why, but it seems that the > IRQ_TINT1_TINT34 interrupt for timer 1 needs to be handled as a > level irq, not edge like all others.
Not sure of the history myself. This has been this way since beginning of DaVinci support in kernel. > > This timer is used by the dsp on dm64* boards only. This would be T1_TOP in code, which is actually marked as unused. T1_BOT is the one used for DSPs. > > Let's move the handler setup out of the aintc driver where it's lived > since the beginning and into the dm64* SoC-specific files where it > belongs. > > Signed-off-by: Bartosz Golaszewski <[email protected]> > --- > arch/arm/mach-davinci/dm644x.c | 4 ++++ > arch/arm/mach-davinci/dm646x.c | 4 ++++ > arch/arm/mach-davinci/irq.c | 1 - I think this should be done for DM355 too? Thanks, Sekhar
