On Tue, Feb 12, 2019 at 06:14:18AM -0800, Matthew Wilcox wrote:
> On Tue, Feb 12, 2019 at 03:59:50PM +0200, Mike Rapoport wrote:
> > -static void * __init get_memblock(unsigned long size)
> > -{
> > - static phys_addr_t search_addr __initdata;
> > - phys_addr_t phys;
> > -
> > - if (!search_addr)
> > - search_addr = PAGE_ALIGN(__pa((unsigned long) &_end));
> > - search_addr = ALIGN(search_addr, size);
> > - while (!memblock_is_region_memory(search_addr, size) ||
> > - memblock_is_region_reserved(search_addr, size)) {
> > - search_addr += size;
> > - }
> > - phys = search_addr;
>
> This implies to me that the allocation will be 'size' aligned.
>
> > if (!pmd) {
> > - pmd = (pmd_t *) get_memblock(PAGE_SIZE << PMD_ORDER);
> > + pmd = memblock_alloc(PAGE_SIZE << PMD_ORDER,
> > + SMP_CACHE_BYTES);
>
> So why would this only need to be cacheline aligned? It's pretty common
> for hardware to require that pgd/pud/pmd/pte tables be naturally aligned.
>
> > @@ -700,7 +683,10 @@ static void __init pagetable_init(void)
> > }
> > #endif
> >
> > - empty_zero_page = get_memblock(PAGE_SIZE);
> > + empty_zero_page = memblock_alloc(PAGE_SIZE, SMP_CACHE_BYTES);
>
> ... and surely the zero page also needs to be page aligned, by definition.
Right, I've completely missed the alignment. Will fix.
--
Sincerely yours,
Mike.
