On 2019/2/4 20:13, Shameer Kolothum wrote: > HiSilicon erratum 162001800 describes the limitation of > SMMUv3 PMCG implementation on HiSilicon Hip08 platforms. > > On these platforms, the PMCG event counter registers > (SMMU_PMCG_EVCNTRn) are read only and as a result it > is not possible to set the initial counter period value > on event monitor start. > > To work around this, the current value of the counter > is read and used for delta calculations. OEM information > from ACPI header is used to identify the affected hardware > platforms. > > Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com> > --- > drivers/acpi/arm64/iort.c | 16 ++++++++++++++- > drivers/perf/arm_smmuv3_pmu.c | 48 > ++++++++++++++++++++++++++++++++++++------- > include/linux/acpi_iort.h | 1 + > 3 files changed, 57 insertions(+), 8 deletions(-)
For this patch, Reviewed-by: Hanjun Guo <hanjun....@linaro.org> Thanks Hanjun
