-----Original Message----- From: Lorenzo Pieralisi <lorenzo.pieral...@arm.com> Sent: 2019年2月6日 2:03 To: Xiaowei Bao <xiaowei....@nxp.com> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li <leoyang...@nxp.com>; kis...@ti.com; a...@arndb.de; gre...@linuxfoundation.org; M.h. Lian <minghuan.l...@nxp.com>; Mingkai Hu <mingkai...@nxp.com>; Roy Zang <roy.z...@nxp.com>; kstew...@linuxfoundation.org; cyrille.pitc...@free-electrons.com; pombreda...@nexb.com; shawn....@rock-chips.com; linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linuxppc-...@lists.ozlabs.org Subject: Re: [PATCHv6 1/4] dt-bindings: add DT binding for the layerscape PCIe controller with EP mode
On Tue, Jan 22, 2019 at 02:33:25PM +0800, Xiaowei Bao wrote: > Add the documentation for the Device Tree binding for the layerscape > PCIe controller with EP mode. > > Signed-off-by: Xiaowei Bao <xiaowei....@nxp.com> > Reviewed-by: Minghuan Lian <minghuan.l...@nxp.com> > Reviewed-by: Zhiqiang Hou <zhiqiang....@nxp.com> > Reviewed-by: Rob Herring <robh...@kernel.org> > --- > v2: > - Add the SoC specific compatibles. > v3: > - modify the commit message. > v4: > - no change. > v5: > - no change. > v6: > - no change. > > .../devicetree/bindings/pci/layerscape-pci.txt | 3 +++ > 1 files changed, 3 insertions(+), 0 deletions(-) Applied the series to pci/layerscape for v5.1, thanks. [Xiaowei Bao] Hi Lorenzo, thank a lot. Lorenzo > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > index 9b2b8d6..e20ceaa 100644 > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > @@ -13,6 +13,7 @@ information. > > Required properties: > - compatible: should contain the platform identifier such as: > + RC mode: > "fsl,ls1021a-pcie" > "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" > "fsl,ls2088a-pcie" > @@ -20,6 +21,8 @@ Required properties: > "fsl,ls1046a-pcie" > "fsl,ls1043a-pcie" > "fsl,ls1012a-pcie" > + EP mode: > + "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" > - reg: base addresses and lengths of the PCIe controller register blocks. > - interrupts: A list of interrupt outputs of the controller. Must contain an > entry for each entry in the interrupt-names property. > -- > 1.7.1 >
