Quoting Paul Cercueil (2019-01-27 18:09:20) > Take a parent rate of 180 MHz, and a requested rate of 4.285715 MHz. > This results in a theorical divider of 41.999993 which is then rounded > up to 42. The .round_rate function would then return (180 MHz / 42) as > the clock, rounded down, so 4.285714 MHz. > > Calling clk_set_rate on 4.285714 MHz would round the rate again, and > give a theorical divider of 42,0000028, now rounded up to 43, and the > rate returned would be (180 MHz / 43) which is 4.186046 MHz, aka. not > what we requested. > > Fix this by rounding up the divisions. > > Signed-off-by: Paul Cercueil <p...@crapouillou.net> > Tested-by: Maarten ter Huurne <maar...@treewalker.org> > Cc: <sta...@vger.kernel.org> > ---
Applied to clk-next
