I have the latest BIOS update for my laptop which is buggy I suppose.
There has been only one update this year if my memory serves me
correctly. Is there any hope to fix this or am I at the mercy of the
hardware vendor which apparenlty doesn't look like they will release
another patch this year. Please forgive me as I am not a kernel
developer but a concerned user. I've sacrificed ACPI in favor of SMP
at this point, I don't know what it's buying me but the kernel boots
and works fine with the draw back that I have no ACPI and I have to
manually power the computer down by pressing the power button when it
halts. I can live with that if that is the solution but I haven't
really tracked as far as the high level dev stuff goes in this thread
and don't know what the solution might be.

On 8/8/07, Joachim Deguara <[EMAIL PROTECTED]> wrote:
> On Wednesday 08 August 2007 02:06:31 Andi Kleen wrote:
> > On Tue, Aug 07, 2007 at 06:15:37PM -0400, Cal Peake wrote:
> > > On Fri, 3 Aug 2007, Linus Torvalds wrote:
> > > > > MSR_K8_ENABLE_C1E lo == 0x04c14015
> > > > > MSR_K8_ENABLE_C1E hi == 0x00000000
> > > > > lo & ENABLE_C1E_MASK == 0
> > > >
> > > > And yeah, that claims that C1E is not on, but:
> > > > > amd_apic_timer_broken: forcing return value of 1
> > >
> > > So it seems my initial debugging report was, err, incomplete. I failed to
> > > notice that the amd_apic_timer_broken function was getting called twice,
> > > once for each core.
> > >
> > > The second call shows this:
> > >
> > >   MSR_K8_ENABLE_C1E == 0x14c14015
> >
> > Ah interesting. Ok finally that all starts making sense.
> >
> > Not sure why the MSR varies between cores though.
>
> This is a BIOS bug as the BIOS should have programmed the MSR the same for
> both cores.  See section 10.2.4 of the Rev F BKDG [1] (10.2.4.1 talks about
> the SMI case but a newer version of the doc not yet release has similar
> wording about both cores needing to have the bit set for the chipset case).
>
> -Joachim
>
> [1]
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
>
>
>
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