[PATCH RESEND V2 1/2] clk: imx8mq: add GPIO clocks to clock tree

[Anson Huang]

i.MX8MQ has clock gate for each GPIO bank, add them
into clock tree for GPIO driver to manage.

Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
No changes, just rebase to clk-next.
---
 drivers/clk/imx/clk-imx8mq.c             | 5 +++++
 include/dt-bindings/clock/imx8mq-clock.h | 8 +++++++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 01c771f..789dc8e 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -510,6 +510,11 @@ static int imx8mq_clocks_probe(struct platform_device 
*pdev)
        clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", 
"ecspi2", base + 0x4080, 0);
        clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", 
"ecspi3", base + 0x4090, 0);
        clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", 
"enet_axi", base + 0x40a0, 0);
+       clks[IMX8MQ_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", 
"ipg_root", base + 0x40b0, 0);
+       clks[IMX8MQ_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", 
"ipg_root", base + 0x40c0, 0);
+       clks[IMX8MQ_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", 
"ipg_root", base + 0x40d0, 0);
+       clks[IMX8MQ_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", 
"ipg_root", base + 0x40e0, 0);
+       clks[IMX8MQ_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", 
"ipg_root", base + 0x40f0, 0);
        clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", 
base + 0x4100, 0);
        clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", 
base + 0x4170, 0);
        clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", 
base + 0x4180, 0);
diff --git a/include/dt-bindings/clock/imx8mq-clock.h 
b/include/dt-bindings/clock/imx8mq-clock.h
index 491e39c..b58cc64 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -394,5 +394,11 @@
 #define IMX8MQ_CLK_CLKO1                       268
 #define IMX8MQ_CLK_ARM                         269
 
-#define IMX8MQ_CLK_END                         270
+#define IMX8MQ_CLK_GPIO1_ROOT                  270
+#define IMX8MQ_CLK_GPIO2_ROOT                  271
+#define IMX8MQ_CLK_GPIO3_ROOT                  272
+#define IMX8MQ_CLK_GPIO4_ROOT                  273
+#define IMX8MQ_CLK_GPIO5_ROOT                  274
+
+#define IMX8MQ_CLK_END                         275
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
-- 
2.7.4