i.MX7ULP has a MMDC module to control DDR, it reuses
i.MX6Q's MMDC module, add support for it.

Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
 arch/arm/boot/dts/imx7ulp.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index fca6e50..fca4a01 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -286,6 +286,12 @@
                        status = "disabled";
                };
 
+               mmdc: mmdc@40ab0000 {
+                       compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
+                       reg = <0x40ab0000 0x1000>;
+                       clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
+               };
+
                iomuxc1: pinctrl@40ac0000 {
                        compatible = "fsl,imx7ulp-iomuxc1";
                        reg = <0x40ac0000 0x1000>;
-- 
2.7.4

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