Resend clock patches from v4 based on v5.0-rc1. The whole series now is composed of a fix for PLL tuner (PATCH 1), clock common changes for both MT8183 & MT6765 (PATCH 2-3), clock support of MT8183 (PATCH 4-8) and resend a clock patch long time ago(PTACH 9).
changes since v4: - refine for the fix of PLL tuner(PATCH 1). - add configurable pcw_chg_reg for MT8183 and the following IC(PATCH 7). changes sinve v3: - add fix tag. - small change of mtk_clk_mux data structure. - use of_property_for_each_string to iterate dependent subsys clock of power domain. - document critical clocks. - reduce some clock register error log. - few coding style fix. changes sinve v2: - refine for implementation consistency of mtk clk mux. - separate the onoff API into enable/disable API for mtk scpsys. - resend a patch about PLL rate changing. changes since v1: - refine for better code quality. - some minor bug fix of clock part, like incorrect control address and missing clocks.
