Am Donnerstag, den 07.03.2019, 03:41 +0000 schrieb Anson Huang:
> There is another 27MHz OSC inside i.MX8MQ's display block and
> it can be one of reference clocks of all PLLs, add it into clock
> tree and also add it as PLL's reference clock.
>
> Signed-off-by: Anson Huang <anson.hu...@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mq.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index a9b3888..bb1bf9b 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -26,7 +26,7 @@ static u32 share_count_nand;
>
> static struct clk *clks[IMX8MQ_CLK_END];
>
> -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy",
> "dummy", };
> +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m",
> "osc_hdmi_phy_27m", "dummy", };
> static const char * const arm_pll_bypass_sels[] = {"arm_pll",
> "arm_pll_ref_sel", };
> static const char * const gpu_pll_bypass_sels[] = {"gpu_pll",
> "gpu_pll_ref_sel", };
> static const char * const vpu_pll_bypass_sels[] = {"vpu_pll",
> "vpu_pll_ref_sel", };
> @@ -281,6 +281,7 @@ static int imx8mq_clocks_probe(struct platform_device
> *pdev)
> clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(np, "ckil");
> clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(np, "osc_25m");
> clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(np, "osc_27m");
> + clks[IMX8MQ_CLK_HDMI_PHY_27M] = of_clk_get_by_name(np,
> "osc_hdmi_phy_27m");
This is not acceptable. This adds a new required clock input, without
bothering to add the corresponding binding information or thinking
about backwards compatibility. At this point there are existing DTs out
there, which don't provide this required clock, which will cause a full
boot regression. This can only be an optional clock input at this
point.
Regards,
Lucas
> clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
> clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
> clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
