Re: [PATCH v2] PCI: qcom: Use default config space read function

[Marc Gonzalez]

On 14/03/2019 12:10, Srinivas Kandagatla wrote:

> Here is the output: https://paste.ubuntu.com/p/kFWZ4kXCxT/

Could you test the following patch:
And report boot log as well as output of lspci -vv ?

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c 
b/drivers/pci/controller/dwc/pcie-designware-host.c
index 45ff5e4f8af6..aca656eff8ca 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -727,7 +727,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
        /* Enable write permission for the DBI read-only register */
        dw_pcie_dbi_ro_wr_en(pci);
        /* Program correct class for RC */
+       dw_pcie_rd_own_conf(pp, PCI_CLASS_REVISION, 4, &val);
+       printk("\tBEFORE: CLASS/REV=%08x\n", val);
        dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+       dw_pcie_rd_own_conf(pp, PCI_CLASS_REVISION, 4, &val);
+       printk("\t AFTER: CLASS/REV=%08x\n", val);
        /* Better disable write permission right after the update */
        dw_pcie_dbi_ro_wr_dis(pci);
 
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c 
b/drivers/pci/controller/dwc/pcie-qcom.c
index d185ea5fe996..c5e16f9aaf44 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1129,25 +1129,8 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
        return ret;
 }
 
-static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
-                                u32 *val)
-{
-       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-
-       /* the device class is not reported correctly from the register */
-       if (where == PCI_CLASS_REVISION && size == 4) {
-               *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
-               *val &= 0xff;   /* keep revision id */
-               *val |= PCI_CLASS_BRIDGE_PCI << 16;
-               return PCIBIOS_SUCCESSFUL;
-       }
-
-       return dw_pcie_read(pci->dbi_base + where, size, val);
-}
-
 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
        .host_init = qcom_pcie_host_init,
-       .rd_own_conf = qcom_pcie_rd_own_conf,
 };
 
 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
@@ -1299,6 +1282,13 @@ static int qcom_pcie_probe(struct platform_device *pdev)
        return ret;
 }
 
+static void qcom_fixup_class(struct pci_dev *dev)
+{
+       printk("\tAPPLYING %s\n", __func__);
+       dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class); // 8064
+
 static const struct of_device_id qcom_pcie_match[] = {
        { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
        { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },