On Mon, Mar 18, 2019 at 03:05:09AM +0000, Zhang, Lei wrote:
> Thanks for your comments.
> I also have considered to use MIDR_CPU_VAR_REV macro,
> but the implication of (~MIDR_CPU_VAR_REV(1, 0)) is "NOT v1r0".
> I think it may cause confusion, so I choose the
> simple way (~(0x1 << MIDR_VARIANT_SHIFT)).
I think that either way is just as confusing, and the fact we're
assigning it to a mask (of bits to preserve) should make this clear. For
consistency, I'd prefer to use MIDR_CPU_VAR_REV().
Catalin, are you happy to take the below as a fix for v5.1?
Thanks,
Mark.
---->8----
>From 6439e9c0b1525e9d4c7be65552e6f2b1f9d1dbe0 Mon Sep 17 00:00:00 2001
From: "Okamoto, Takayuki" <tokam...@jp.fujitsu.com>
Date: Fri, 15 Mar 2019 12:22:36 +0000
Subject: [PATCH] arm64: apply workaround on A64FX v1r0
Fujitsu erratum 010001 applies to A64FX v0r0 and v1r0, and we try to
handle either by masking MIDR with MIDR_FUJITSU_ERRATUM_010001_MASK
before comparing it to MIDR_FUJITSU_ERRATUM_010001.
Unfortunately, MIDR_FUJITSU_ERRATUM_010001 is constructed incorrectly
using MIDR_VARIANT(), which is intended to extract the variant field
from MIDR_EL1, rather than generate the field in-place. This results in
MIDR_FUJITSU_ERRATUM_010001 being all-ones, and we only match A64FX
v0r0.
This patch uses MIDR_CPU_VAR_REV() to generate an in-place mask for the
variant field, ensuring the we match both v0r0 and v1r0.
Fixes: 3e32131abc311a5c ("arm64: Add workaround for Fujitsu A64FX erratum
010001")
Signed-off-by: Zhang Lei <zhang....@jp.fujitsu.com>
[Mark: use MIDR_CPU_VAR_REV(), reword commit message]
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
---
arch/arm64/include/asm/cputype.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 2afb1338b48a..f3b659587a36 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -129,7 +129,7 @@
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
-#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_VARIANT(1))
+#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
#ifndef __ASSEMBLY__
--
2.11.0
