Re: [PATCH] drivers: clk: zynqmp: Allow zero divisor value

[Stephen Boyd]

Quoting Michal Simek (2019-03-18 05:48:52)
> On 05. 03. 19 0:27, Jolly Shah wrote:
> > From: Rajan Vaja <rajan.v...@xilinx.com>
> > 
> > Zero divider is valid and default for some of ZynqMP
> > clocks. Allow zero divisor when CLK_DIVIDER_ALLOW_ZERO
> > for the clock is set.
> > 
> > Signed-off-by: Rajan Vaja <raj...@xilinx.com>
> > Signed-off-by: Jolly Shah <jol...@xilinx.com>
> > ---
> >  drivers/clk/zynqmp/divider.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> > index a371c66..e146b6f 100644
> > --- a/drivers/clk/zynqmp/divider.c
> > +++ b/drivers/clk/zynqmp/divider.c
> > @@ -76,6 +76,13 @@ static unsigned long 
> > zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
> >       else
> >               value = div >> 16;
> >  
> > +     if (!value) {
> > +             WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
> > +                  "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
> > +                  clk_name);
> > +             return parent_rate;
> > +     }
> > +
> >       return DIV_ROUND_UP_ULL(parent_rate, value);
> >  }
> >  
> > 
> 
> Stephen: Do you want to take it via your tree?
> 

Sure.