clk_gate_ufs_subsys is a system bus clock, turning off it will
introduce lockup issue during system suspend flow. Let's mark
clk_gate_ufs_subsys as critical clock, thus keeps it on during
system suspend and resume.
Fixes: d374e6fd5088 ("clk: hisilicon: Add clock driver for hi3660 SoC")
Cc: sta...@vger.kernel.org
Cc: Zhong Kaihua <zhongkai...@huawei.com>
Cc: John Stultz <john.stu...@linaro.org>
Cc: Zhangfei Gao <zhangfei....@linaro.org>
Suggested-by: Dong Zhang <zhangdon...@hisilicon.com>
Signed-off-by: Leo Yan <leo....@linaro.org>
---
drivers/clk/hisilicon/clk-hi3660.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/hisilicon/clk-hi3660.c
b/drivers/clk/hisilicon/clk-hi3660.c
index f40419959656..32ba80181cc6 100644
--- a/drivers/clk/hisilicon/clk-hi3660.c
+++ b/drivers/clk/hisilicon/clk-hi3660.c
@@ -164,7 +164,7 @@ static const struct hisi_gate_clock
hi3660_crgctrl_gate_sep_clks[] = {
{ HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2",
"clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, },
{ HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus",
- CLK_SET_RATE_PARENT, 0x50, 21, 0, },
+ CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x50, 21, 0, },
{ HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
CLK_SET_RATE_PARENT, 0x50, 28, 0, },
{ HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
--
2.17.1
