On Mon, Mar 25, 2019 at 06:16:48PM +0100, Borislav Petkov wrote:
> From: Borislav Petkov <[email protected]>
>
> This is an AMD-specific MSR. Put it where it belongs.
>
> Signed-off-by: Borislav Petkov <[email protected]>
> Tested-by: Yazen Ghannam <[email protected]>
> ---
> arch/x86/kvm/svm.c | 14 ++++++++++++++
> arch/x86/kvm/x86.c | 12 ------------
> 2 files changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index b5b128a0a051..00eb44a2a377 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -4201,6 +4201,9 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct
> msr_data *msr_info)
> case MSR_F10H_DECFG:
> msr_info->data = svm->msr_decfg;
> break;
> + case MSR_K7_HWCR:
> + msr_info->data = 0;
> + break;
> default:
> return kvm_get_msr_common(vcpu, msr_info);
> }
> @@ -4405,6 +4408,17 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct
> msr_data *msr)
> svm->msr_decfg = data;
> break;
> }
> + case MSR_K7_HWCR:
> + data &= ~(u64)0x40; /* ignore flush filter disable */
> + data &= ~(u64)0x100; /* ignore ignne emulation enable */
> + data &= ~(u64)0x8; /* ignore TLB cache disable */
> + data &= ~(u64)0x40000; /* ignore Mc status write enable */
> + if (data != 0) {
> + vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
> + data);
> + return 1;
> + }
> + break;
> case MSR_IA32_APICBASE:
> if (kvm_vcpu_apicv_active(vcpu))
> avic_update_vapic_bar(to_svm(vcpu), data);
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 65e4559eef2f..e53d13cfceba 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -2445,17 +2445,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct
> msr_data *msr_info)
> break;
> case MSR_EFER:
> return set_efer(vcpu, data);
> - case MSR_K7_HWCR:
> - data &= ~(u64)0x40; /* ignore flush filter disable */
> - data &= ~(u64)0x100; /* ignore ignne emulation enable */
> - data &= ~(u64)0x8; /* ignore TLB cache disable */
> - data &= ~(u64)0x40000; /* ignore Mc status write enable */
> - if (data != 0) {
> - vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
> - data);
> - return 1;
> - }
> - break;
> case MSR_FAM10H_MMIO_CONF_BASE:
> if (data != 0) {
> vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
> @@ -2724,7 +2713,6 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct
> msr_data *msr_info)
> case MSR_K8_SYSCFG:
> case MSR_K8_TSEG_ADDR:
> case MSR_K8_TSEG_MASK:
> - case MSR_K7_HWCR:
Won't this prevent emulating an AMD guest on Intel hardware, e.g. due to
injecting #GPs during boot? Keeping support in kvm_{get,set}_msr_common
doesn't preclude svm_{get,set}_msr() from having SVM-specific handling for
the MSR.
> case MSR_VM_HSAVE_PA:
> case MSR_K8_INT_PENDING_MSG:
> case MSR_AMD64_NB_CFG:
> --
> 2.21.0
>
