On 26/03/2019 14:24, Marc Gonzalez wrote:
> +static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
> + .tx_tbl = msm8998_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
> + .rx_tbl = msm8998_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
> + .pcs_tbl = msm8998_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
Looking more closely at the code downstream, it looks like the
reset situation is slightly different. Let me spin a v3.
Regards.
