Add the idle state cpu-sleep to each core. This idle state
makes use of 'local-wakeup-poke' property which basically tells
the cpuidle-arm driver to enable the poking for this state.
Signed-off-by: Abel Vesa <abel.v...@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 230f198..8b7303d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -84,6 +84,22 @@
#address-cells = <1>;
#size-cells = <0>;
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010033>;
+ local-timer-stop;
+ local-wakeup-poke;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+
+
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
@@ -94,6 +110,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_1: cpu@1 {
@@ -106,6 +123,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_2: cpu@2 {
@@ -118,6 +136,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_3: cpu@3 {
@@ -130,6 +149,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_L2: l2-cache0 {
--
2.7.4
