Manipulating $(MAKECMDGOALS) for sub-make seems odd to me.
[1] 'make O=foo sub-make' is turned into 'make O=foo', which builds
the default targets. It would make sense to terminate the build with:
*** No rule to make target 'sub-make'. Stop.
[2] 'make O=foo defconfig _all' is turned into 'make O=foo defconfig',
which changes the behavior.
Let's pass $(MAKECMDGOALS) as is.
Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index 92ad066..9cbd367 100644
--- a/Makefile
+++ b/Makefile
@@ -168,7 +168,7 @@ $(filter-out _all sub-make $(lastword $(MAKEFILE_LIST)),
$(MAKECMDGOALS)) _all:
sub-make:
$(Q)$(MAKE) \
$(if $(KBUILD_OUTPUT),-C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR)) \
- -f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS))
+ -f $(CURDIR)/Makefile $(MAKECMDGOALS)
endif # need-sub-make
endif # sub_make_done
--
2.7.4
