Return status based on ssbd_state and the arm64 SSBS feature. If
the mitigation is disabled, or the firmware isn't responding then
return the expected machine state based on a whitelist of known
good cores.
Given a heterogeneous machine, the overall machine vulnerability
must be a tristate to assure any vulnerable cores transition to
vulnerable and stay there. Further, we delay transitioning to
vulnerable until we know the firmware isn't responding to avoid a
case where we miss the whitelist, but the firmware goes ahead and
reports the core is not vulnerable.
Signed-off-by: Jeremy Linton <jeremy.lin...@arm.com>
---
arch/arm64/kernel/cpu_errata.c | 62 ++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 6958dcdabf7d..a1f3188c7be0 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -278,6 +278,13 @@ static int detect_harden_bp_fw(void)
DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
+static enum {SSB_UNSET, SSB_SAFE, SSB_UNSAFE} __ssb_safe = SSB_UNSET;
+
+static inline void ssb_safe(void)
+{
+ if (__ssb_safe == SSB_UNSET)
+ __ssb_safe = SSB_SAFE;
+}
static const struct ssbd_options {
const char *str;
@@ -383,16 +390,25 @@ static bool has_ssbd_mitigation(const struct
arm64_cpu_capabilities *entry,
struct arm_smccc_res res;
bool required = true;
s32 val;
+ bool this_cpu_safe = false;
WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
if (this_cpu_has_cap(ARM64_SSBS)) {
required = false;
+ ssb_safe();
goto out_printmsg;
}
+ if (is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list)) {
+ ssb_safe();
+ this_cpu_safe = true;
+ }
+
if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
ssbd_state = ARM64_SSBD_UNKNOWN;
+ if (!this_cpu_safe)
+ __ssb_safe = SSB_UNSAFE;
return false;
}
@@ -409,6 +425,8 @@ static bool has_ssbd_mitigation(const struct
arm64_cpu_capabilities *entry,
default:
ssbd_state = ARM64_SSBD_UNKNOWN;
+ if (!this_cpu_safe)
+ __ssb_safe = SSB_UNSAFE;
return false;
}
@@ -417,23 +435,31 @@ static bool has_ssbd_mitigation(const struct
arm64_cpu_capabilities *entry,
switch (val) {
case SMCCC_RET_NOT_SUPPORTED:
ssbd_state = ARM64_SSBD_UNKNOWN;
+ if (!this_cpu_safe)
+ __ssb_safe = SSB_UNSAFE;
return false;
+ /* machines with mixed mitigation requirements must not return this */
case SMCCC_RET_NOT_REQUIRED:
pr_info_once("%s mitigation not required\n", entry->desc);
ssbd_state = ARM64_SSBD_MITIGATED;
+ ssb_safe();
return false;
case SMCCC_RET_SUCCESS:
+ __ssb_safe = SSB_UNSAFE;
required = true;
break;
case 1: /* Mitigation not required on this CPU */
required = false;
+ ssb_safe();
break;
default:
WARN_ON(1);
+ if (!this_cpu_safe)
+ __ssb_safe = SSB_UNSAFE;
return false;
}
@@ -474,6 +500,14 @@ static bool has_ssbd_mitigation(const struct
arm64_cpu_capabilities *entry,
return required;
}
+/* known invulnerable cores */
+static const struct midr_range arm64_ssb_cpus[] = {
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
+ {},
+};
+
static void __maybe_unused
cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
{
@@ -769,6 +803,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
.capability = ARM64_SSBD,
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
.matches = has_ssbd_mitigation,
+ .midr_range_list = arm64_ssb_cpus,
},
#ifdef CONFIG_ARM64_ERRATUM_1188873
{
@@ -807,3 +842,30 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct
device_attribute *attr,
return sprintf(buf, "Vulnerable\n");
}
+
+ssize_t cpu_show_spec_store_bypass(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ /*
+ * Two assumptions: First, ssbd_state reflects the worse case
+ * for heterogeneous machines, and that if SSBS is supported its
+ * supported by all cores.
+ */
+ switch (ssbd_state) {
+ case ARM64_SSBD_MITIGATED:
+ return sprintf(buf, "Not affected\n");
+
+ case ARM64_SSBD_KERNEL:
+ case ARM64_SSBD_FORCE_ENABLE:
+ if (cpus_have_cap(ARM64_SSBS))
+ return sprintf(buf, "Not affected\n");
+ if (IS_ENABLED(CONFIG_ARM64_SSBD))
+ return sprintf(buf,
+ "Mitigation: Speculative Store Bypass disabled\n");
+ }
+
+ if (__ssb_safe == SSB_SAFE)
+ return sprintf(buf, "Not affected\n");
+
+ return sprintf(buf, "Vulnerable\n");
+}
--
2.20.1
