Quoting Weiyi Lu (2019-03-04 21:05:38) > From: Owen Chen <owen.c...@mediatek.com> > > PLLs with tuner_en bit, such as APLL1, need to disable > tuner_en before apply new frequency settings, or the new frequency > settings (pcw) will not be applied. > The tuner_en bit will be disabled during changing PLL rate > and be restored after new settings applied. > > Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support) > Cc: <sta...@vger.kernel.org> > Signed-off-by: Owen Chen <owen.c...@mediatek.com> > Signed-off-by: Weiyi Lu <weiyi...@mediatek.com> > ---
Applied to clk-next
