On 08/04/2019 17:49, Marc Zyngier wrote: > Instead of always going via arch_counter_get_cntvct_stable to > access the counter workaround, let's have arch_timer_read_counter > to point to the right method. > > For that, we need to track whether any CPU in the system has a > workaround for the counter. This is done by having an atomic > variable tracking this. > > Signed-off-by: Marc Zyngier <[email protected]> > ---
[ ... ] > + > /* > * Default to cp15 based access because arm64 uses this function for > * sched_clock() before DT is probed and the cp15 method is guaranteed > @@ -372,6 +392,7 @@ static u32 notrace sun50i_a64_read_cntv_tval_el0(void) > DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, > timer_unstable_counter_workaround); > EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); > > +static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0); Wouldn't make sense to READ_ONCE / WRITE_ONCE instead of using an atomic? > static void erratum_set_next_event_tval_generic(const int access, unsigned > long evt, > struct clock_event_device *clk) > @@ -550,6 +571,9 @@ void arch_timer_enable_workaround(const struct > arch_timer_erratum_workaround *wa > per_cpu(timer_unstable_counter_workaround, i) = wa; > } > > + if (wa->read_cntvct_el0 || wa->read_cntpct_el0) > + atomic_set(&timer_unstable_counter_workaround_in_use, 1); > + [ ... ] -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
