On Tue, Apr 09, 2019 at 11:06:43AM +0100, Dragan Cvetic wrote: > Add the Soft Decision Forward Error Correction (SDFEC) Engine > bindings which is available for the Zynq UltraScale+ RFSoC > FPGA's. > > Signed-off-by: Dragan Cvetic <dragan.cve...@xilinx.com> > Signed-off-by: Derek Kiernan <derek.kier...@xilinx.com> > --- > .../devicetree/bindings/misc/xlnx,sd-fec.txt | 58 > ++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt
Don't you have to send new bindings to the DT maintainers? thanks, greg k-h
