The patch

   spi: expand mode support

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 937e6d756422637eeb212c645ded69569a67fabc Mon Sep 17 00:00:00 2001
From: Sowjanya Komatineni <skomatin...@nvidia.com>
Date: Mon, 15 Apr 2019 14:30:27 -0700
Subject: [PATCH] spi: expand mode support

This patch changes mode and mode_bits from u16 to u32 to allow more
mode configurations.

Signed-off-by: Sowjanya Komatineni <skomatin...@nvidia.com>
Signed-off-by: Mark Brown <broo...@kernel.org>
---
 include/linux/spi/spi.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 589f9dc9ac2b..053abd22ad31 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -143,7 +143,7 @@ struct spi_device {
        u32                     max_speed_hz;
        u8                      chip_select;
        u8                      bits_per_word;
-       u16                     mode;
+       u32                     mode;
 #define        SPI_CPHA        0x01                    /* clock phase */
 #define        SPI_CPOL        0x02                    /* clock polarity */
 #define        SPI_MODE_0      (0|0)                   /* (original MicroWire) 
*/
@@ -443,7 +443,7 @@ struct spi_controller {
        u16                     dma_alignment;
 
        /* spi_device.mode flags understood by this controller driver */
-       u16                     mode_bits;
+       u32                     mode_bits;
 
        /* bitmask of supported bits_per_word for transfers */
        u32                     bits_per_word_mask;
@@ -1291,7 +1291,7 @@ struct spi_board_info {
        /* mode becomes spi_device.mode, and is essential for chips
         * where the default of SPI_CS_HIGH = 0 is wrong.
         */
-       u16             mode;
+       u32             mode;
 
        /* ... may need additional spi_device chip config data here.
         * avoid stuff protocol drivers can set; but include stuff
-- 
2.20.1

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