On Thu, May 02, 2019 at 10:50:12AM +0530, Yash Shah wrote: > On Thu, May 2, 2019 at 6:11 AM Rob Herring <r...@kernel.org> wrote: > > > > On Tue, Apr 30, 2019 at 09:50:45AM +0530, Yash Shah wrote: > > > On Fri, Apr 26, 2019 at 3:04 PM Sudeep Holla <sudeep.ho...@arm.com> wrote: > > > > > > > > On Fri, Apr 26, 2019 at 11:20:17AM +0530, Yash Shah wrote: > > > > > On Thu, Apr 25, 2019 at 3:43 PM Sudeep Holla <sudeep.ho...@arm.com> > > > > > wrote: > > > > > > > > > > > > On Thu, Apr 25, 2019 at 11:24:55AM +0530, Yash Shah wrote: > > > > > > > Add device tree bindings for SiFive FU540 L2 cache controller > > > > > > > driver > > > > > > > > > > > > > > Signed-off-by: Yash Shah <yash.s...@sifive.com> > > > > > > > --- > > > > > > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 > > > > > > > ++++++++++++++++++++++ > > > > > > > 1 file changed, 53 insertions(+) > > > > > > > create mode 100644 > > > > > > > Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > > > > > > > > diff --git > > > > > > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > new file mode 100644 > > > > > > > index 0000000..15132e2 > > > > > > > --- /dev/null > > > > > > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > @@ -0,0 +1,53 @@ > > > > > > > +SiFive L2 Cache Controller > > > > > > > +-------------------------- > > > > > > > +The SiFive Level 2 Cache Controller is used to provide access to > > > > > > > fast copies > > > > > > > +of memory for masters in a Core Complex. The Level 2 Cache > > > > > > > Controller also > > > > > > > +acts as directory-based coherency manager. > > > > > > > + > > > > > > > +Required Properties: > > > > > > > +-------------------- > > > > > > > +- compatible: Should be "sifive,fu540-c000-ccache" > > > > > > > + > > > > > > > +- cache-block-size: Specifies the block size in bytes of the > > > > > > > cache > > > > > > > + > > > > > > > +- cache-level: Should be set to 2 for a level 2 cache > > > > > > > + > > > > > > > +- cache-sets: Specifies the number of associativity sets of the > > > > > > > cache > > > > > > > + > > > > > > > +- cache-size: Specifies the size in bytes of the cache > > > > > > > + > > > > > > > +- cache-unified: Specifies the cache is a unified cache > > > > > > > + > > > > > > > +- interrupt-parent: Must be core interrupt controller > > > > > > > + > > > > > > > +- interrupts: Must contain 3 entries (DirError, DataError and > > > > > > > DataFail signals) > > > > > > > + > > > > > > > +- reg: Physical base address and size of L2 cache controller > > > > > > > registers map > > > > > > > + > > > > > > > +- reg-names: Should be "control" > > > > > > > + > > > > > > > > > > > > It would be good if you mark the properties that are present in DT > > > > > > specification and those that are added for sifive,fu540-c000-ccache > > > > > > > > > > I believe there isn't any property which is added explicitly for > > > > > sifive,fu540-c000-ccache. > > > > > > > > > > > > > reg and interrupts are generally optional for normal cache and may be > > > > required for cache controller like this. DT specification[1] covers > > > > only caches and not cache controllers. > > > > > > Are you suggesting something like this: > > > > > > Required Properties: > > > -------------------- > > > Standard Properties: > > > > I don't think we need this separation. > > Ok. Won't include this "Standard/Non-standard properties" separation > in the next revision of this patch. >
Sorry if I created confusion. I just wanted a note saying all the properties in ePAPR/DeviceTree specification applies for this platform. That would help me check if the standard cacheinfo infrastruction works as is or not. -- Regards, Sudeep
