The config0 register in the Xburst always reports a MIPS32r2
ISA, but not all of them support it.

Signed-off-by: Paul Cercueil <p...@crapouillou.net>
---
 arch/mips/jz4740/setup.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
index 7e63c54eb8d2..2508c026bdfa 100644
--- a/arch/mips/jz4740/setup.c
+++ b/arch/mips/jz4740/setup.c
@@ -64,6 +64,7 @@ static unsigned long __init get_board_mach_type(const void 
*fdt)
 
 void __init plat_mem_setup(void)
 {
+       struct cpuinfo_mips *c = &current_cpu_data;
        int offset;
        void *dtb;
 
@@ -81,6 +82,18 @@ void __init plat_mem_setup(void)
                jz4740_detect_mem();
 
        mips_machtype = get_board_mach_type(dtb);
+
+       switch (mips_machtype) {
+       case MACH_INGENIC_JZ4740:
+               /*
+                * The config0 register in the Xburst always reports a MIPS32r2
+                * ISA, but not all of them support it.
+                */
+               c->isa_level &= ~MIPS_CPU_ISA_M32R2;
+               break;
+       default:
+               break;
+       }
 }
 
 void __init device_tree_init(void)
-- 
2.21.0.593.g511ec345e18

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