On Fri, May 17, 2019 at 10:26:49AM -0700, Luck, Tony wrote: > Which is a quirk for some models where we don't want to do > the "write all 1s and see what sticks"
Ok, then we have to do what you suggested yesterday. I've added a short comment so that I don't get lost again next time. --- diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 5bcecadcf4d9..9056f0a2a90d 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1493,6 +1493,11 @@ static int __mcheck_cpu_mce_banks_init(void) for (i = 0; i < n_banks; i++) { struct mce_bank *b = &mce_banks[i]; + /* + * Init them all, __mcheck_cpu_apply_quirks() is going to apply + * the required vendor quirks before + * __mcheck_cpu_init_clear_banks() does the final bank setup. + */ b->ctl = -1ULL; b->init = 1; } @@ -1562,15 +1567,21 @@ static void __mcheck_cpu_init_generic(void) static void __mcheck_cpu_init_clear_banks(void) { struct mce_bank *mce_banks = this_cpu_read(mce_banks_array); + u64 msrval; int i; for (i = 0; i < this_cpu_read(mce_num_banks); i++) { struct mce_bank *b = &mce_banks[i]; - if (!b->init) - continue; - wrmsrl(msr_ops.ctl(i), b->ctl); - wrmsrl(msr_ops.status(i), 0); + if (b->init) { + /* Check if any bits are implemented in h/w */ + wrmsrl(msr_ops.ctl(i), b->ctl); + rdmsrl(msr_ops.ctl(i), msrval); + + b->init = !!msrval; + + wrmsrl(msr_ops.status(i), 0); + } } } @@ -2095,6 +2106,9 @@ static ssize_t show_bank(struct device *s, struct device_attribute *attr, b = &per_cpu(mce_banks_array, s->id)[bank]; + if (!b->init) + return -ENODEV; + return sprintf(buf, "%llx\n", b->ctl); } @@ -2113,6 +2127,9 @@ static ssize_t set_bank(struct device *s, struct device_attribute *attr, b = &per_cpu(mce_banks_array, s->id)[bank]; + if (!b->init) + return -ENODEV; + b->ctl = new; mce_restart(); -- 2.21.0 -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.