On Wed, 2007-08-22 at 19:03 +0200, Jes Sorensen wrote: > James Bottomley wrote: > > I really don't think a work around for a PCI spec violation belongs in > > the generic DMA code, do you? The correct fix for this should be to set > > the device hints to strict ordering, which presumably altix respects? > > In which case, it sounds like what needs exposing are access to the PCI > > device hints. I believe both PCI-X and PCIe have these hints as > > optional specifiers in the bridges, so it should be in a current Rev of > > the PCI spec. Or are you proposing adding an additional PCI API that > > allows transaction flushes to be inserted into the stream for devices > > and bridges that have already negotiated relaxed ordering? ... in which > > case we need to take this to the PCI list. > > James, > > I don't believe it respects those hints - I agree, it's a pita, but > thats the state of the situation. Even if it did, it would make > performance suck as Jesse also pointed out. > > As I pointed out in my email to Willy is that the NUMA fabric is routed, > there's not one path through the system, which is what makes this > happen.
Hmm, didn't see the email ... but I'm probably not cc'd on all the thread. However ... it isn't that you couldn't do it ... it's that you don't want to do it because it's faster to violate the spec ... like all those nice ATA devices that lie about having a cache and then let you power down with uncommitted data still in it ... they work much faster for HDIO tests ... and who ever switches their box off? James - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
