On Tue, May 21, 2019 at 04:31:22PM -0700, Sowjanya Komatineni wrote:
> Tegra210 and prior Tegra chips have power request signal polarity,
> deep sleep entry and wake related timings which are platform specific
> that should be configured before entering into deep sleep.
>
> Below are the timings specific configurations for deep sleep and wake.
> - Core rail power-on stabilization timer
> - OSC clock stabilization timer after SOC rail power is stabilized.
> - Core power off time is the minimum wake delay to keep the system
> in deep sleep state irrespective of any quick wake event.
>
> These values depends on the discharge time of regulators and turn OFF
> time of the PMIC to allow the complete system to finish entering into
> deep sleep state.
>
> These values vary based on the platform design and are specified
> through the device tree.
>
> This patch has implementation to configure these configurations which
> are must to have for deep sleep state.
>
> Signed-off-by: Sowjanya Komatineni <skomatin...@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 +++++++
> drivers/soc/tegra/pmc.c | 18 ++++++++++++++++++
> 2 files changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
> b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
> index 4dcd0d36189a..7ac5e55a30aa 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
> @@ -266,6 +266,13 @@
>
> pmc@7000e400 {
> nvidia,invert-interrupt;
> + nvidia,suspend-mode = <0>;
> + nvidia,cpu-pwr-good-time = <0>;
> + nvidia,cpu-pwr-off-time = <0>;
> + nvidia,core-pwr-good-time = <4587 3876>;
> + nvidia,core-pwr-off-time = <39065>;
> + nvidia,core-power-req-active-high;
> + nvidia,sys-clock-req-active-high;
> };
>
> /* eMMC */
This hunk looks like maybe it belongs in the last patch?
Thierry
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index 5e68e1de1780..8d225962d136 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -66,6 +66,7 @@
> #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
> #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
> #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
> +#define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
> #define PMC_CNTRL_MAIN_RST BIT(4)
> #define PMC_CNTRL_LATCH_WAKEUPS BIT(5)
>
> @@ -98,6 +99,8 @@
>
> #define PMC_CPUPWRGOOD_TIMER 0xc8
> #define PMC_CPUPWROFF_TIMER 0xcc
> +#define PMC_COREPWRGOOD_TIMER 0x3c
> +#define PMC_COREPWROFF_TIMER 0xe0
>
> #define PMC_PWR_DET_VALUE 0xe4
>
> @@ -2293,6 +2296,7 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = {
> static void tegra20_pmc_init(struct tegra_pmc *pmc)
> {
> u32 value;
> + unsigned long osc, pmu, off;
>
> /* Always enable CPU power request */
> value = tegra_pmc_readl(pmc, PMC_CNTRL);
> @@ -2306,6 +2310,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc)
> else
> value |= PMC_CNTRL_SYSCLK_POLARITY;
>
> + if (pmc->corereq_high)
> + value &= ~PMC_CNTRL_PWRREQ_POLARITY;
> + else
> + value |= PMC_CNTRL_PWRREQ_POLARITY;
> +
> /* configure the output polarity while the request is tristated */
> tegra_pmc_writel(pmc, value, PMC_CNTRL);
>
> @@ -2313,6 +2322,15 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc)
> value = tegra_pmc_readl(pmc, PMC_CNTRL);
> value |= PMC_CNTRL_SYSCLK_OE;
> tegra_pmc_writel(pmc, value, PMC_CNTRL);
> +
> + osc = DIV_ROUND_UP_ULL(pmc->core_osc_time * 8192, 1000000);
> + pmu = DIV_ROUND_UP_ULL(pmc->core_pmu_time * 32768, 1000000);
> + off = DIV_ROUND_UP_ULL(pmc->core_off_time * 32768, 1000000);
> + if (osc && pmu)
> + tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
> + PMC_COREPWRGOOD_TIMER);
> + if (off)
> + tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
> }
>
> static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
> --
> 2.7.4
>
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