On Fri, May 31, 2019 at 1:40 PM Palmer Dabbelt <pal...@sifive.com> wrote:
>
> On Thu, 30 May 2019 15:29:22 PDT (-0700), luke.r.n...@gmail.com wrote:
> > In BPF, 32-bit ALU operations should zero-extend their results into
> > the 64-bit registers.
> >
> > The current BPF JIT on RISC-V emits incorrect instructions that perform
> > sign extension only (e.g., addw, subw) on 32-bit add, sub, lsh, rsh,
> > arsh, and neg. This behavior diverges from the interpreter and JITs
> > for other architectures.
> >
> > This patch fixes the bugs by performing zero extension on the destination
> > register of 32-bit ALU operations.
> >
> > Fixes: 2353ecc6f91f ("bpf, riscv: add BPF JIT for RV64G")
> > Cc: Xi Wang <xi.w...@gmail.com>
> > Signed-off-by: Luke Nelson <luke.r.n...@gmail.com>
>
> Reviewed-by: Palmer Dabbelt <pal...@sifive.com>
>
> Thanks! I'm assuming this is going in through a BPF tree and not the RISC-V
> tree, but LMK if that's not the case.
Applied to bpf tree. Thanks
